Forming grounded through-silicon vias in a semiconductor substrate

ABSTRACT

A method of forming an interposer includes providing a semiconductor substrate, the semiconductor substrate having a front surface and a back surface opposite the front surface; forming one or more through-silicon vias (TSVs) extending from the front surface into the semiconductor substrate; forming an inter-layer dielectric (ILD) layer overlying the front surface of the semiconductor substrate and the one or more TSVs; and forming an interconnect structure in the ILD layer, the interconnect structure electrically connecting the one or more TSVs to the semiconductor substrate.

This application is a reissue application of U.S. Pat. No. 8,872,345.

FIELD

The disclosure relates generally to the fabrication of semiconductordevices and, more particularly, to a method of forming groundedthrough-silicon vias in a semiconductor substrate.

BACKGROUND

Interposers are used for integrated circuit packaging, typically forspace transformation, which is for routing connections betweensemiconductor dies and packaging components. FIG. 1 illustrates across-sectional view of a portion of an interposer 10. Usually,interposer 10 includes a substrate 30, which is typically formed oforganic materials or ceramics. One or more through-silicon vias (TSVs)50 are formed in the substrate 30 for making electrical connections fromone or more semiconductor dies and/or packaging components (not shown).

With the increasing scaling down of integrated circuits and increasingcircuit functionality there is an increased demand for progressivelysmaller linewidths on the interposer. As linewidths shrink, RCtransmission line effects increase due to loading from die/die packageresistance, inductance, and/or capacitance. Moreover, as substrate 30 isnot grounded cross coupling or cross talk between adjacent TSVsincreases as well. Due to this cross-coupling between TSVs, signalstraveling along relatively long interconnections suffer delays and otherforms of distortion. As a result, these signals may become corrupted,slowing operation of integrated circuits or even causing failure. Theseeffects are more pronounced as operating frequencies increase.

BRIEF DESCRIPTION OF DRAWINGS

The features, aspects, and advantages of the disclosure will become morefully apparent from the following detailed description, appended claims,and accompanying drawings in which:

FIG. 1 is a cross-sectional view of a portion of an interposer showingthe problem of low signal integrity resulting from TSV to TSV coupling.

FIGS. 2-6 are cross-sectional views of a portion of an interposer atvarious stages of fabrication according to an exemplary embodiment ofthe present disclosure.

DETAILED DESCRIPTION

In the following description, numerous specific details are set forth toprovide a thorough understanding of embodiments of the presentdisclosure. However, one having an ordinary skill in the art willrecognize that embodiments of the disclosure can be practiced withoutthese specific details. In some instances, well-known structures andprocesses are not described in detail to avoid unnecessarily obscuringembodiments of the present disclosure.

Reference throughout this specification to “one embodiment” or “anembodiment” means that a particular feature, structure, orcharacteristic described in connection with the embodiment is includedin at least one embodiment of the present disclosure. Thus, theappearances of the phrases “in one embodiment” or “in an embodiment” invarious places throughout this specification are not necessarily allreferring to the same embodiment. Furthermore, the particular features,structures, or characteristics may be combined in any suitable manner inone or more embodiments. It should be appreciated that the followingfigures are not drawn to scale; rather, these figures are merelyintended for illustration.

FIGS. 2-6 are cross-sectional views of a portion of an interposer 20 atvarious stages of fabrication according to an exemplary embodiment ofthe present disclosure. It is understood that FIGS. 2-6 have beensimplified for a better understanding of the inventive concepts of thepresent disclosure.

Referring to FIG. 2, the interposer 20 includes a substrate 30 having afront surface 32a and a back surface 32b opposite the front surface 32a.Substrate 30 is formed of silicon, although other semiconductormaterials including group III, group IV, group V elements and silicongermanium (SiGe) may also be used. In alternative embodiments, substrate30 contains commonly used materials such as inorganic and organicmaterials, ceramics, and/or multi-layers thereof.

In an embodiment to form a TSV opening that extends from front surface32a into a portion of the substrate 30, a photoresist layer (not shown)is spin coated over the front surface 32a of substrate 30. Thephotoresist layer is then patterned by exposure, bake, development,and/or other photolithography processes using the patterned photoresistlayer as a masking element to form the TSV opening passing through aportion of the substrate 30. In some embodiments, the TSV opening may beetched using any suitable etching method including, for example, plasmaetch, a chemical wet etch, a laser drill, and/or other suitableprocesses. In an embodiment, the etching process includes a deepreactive ion etching (RIF) process to etch the substrate 30. The etchingprocess may result in an opening having a vertical sidewall profile or atapered sidewall profile.

In another embodiment of forming an opening that is a TSV opening, aphotoresist layer (not shown) may be formed on a hard mask layer (notshown). The photoresist layer is patterned by exposure, bake,developing, and/or other photolithography processes to provide anopening exposing the hard mask layer. The exposed hard mask layer isthen etched, by a wet etch or dry etch process, using the patternedphotoresist layer as a masking element to provide an opening. Using thehard mask layer and the patterned photoresist layer as mask elements, anetching process is performed to etch the exposed substrate 30 formingthe TSV opening.

A Liner layer 40 is thereafter formed over substrate 30. Liner layer 40is conformally deposited on the front surface 32a of the substrate 30and along the sidewalls and bottom of the TSV opening in order toprevent any conducting material from leaching into substrate 30. In someembodiments, the liner layer 40 may be formed of silicon oxide, TEOS(tetraethylorthosilicate) oxide, silicon nitride, polyimide,combinations thereof, or the like. The deposition can be carried outusing any of a variety of techniques, including thermal oxidation, LPCVD(low-pressure chemical vapor deposition), APCVD (atmospheric-pressurechemical vapor deposition), PECVD (plasma-enhanced chemical vapordeposition), and other suitable deposition procedures. For example, anLPCVD or PECVD process with TEOS and O₃ may be employed to form a TEOSoxide film.

Still referring to FIG. 2, a barrier layer 45a is then formed on theliner layer 40, lining the TSV opening. The barrier layer 45a functionsas a diffusion barrier to prevent metal diffusion and as an adhesionlayer between metal and dielectric. In some embodiments, refractorymetals, refractory metal-nitrides, refractory metal-silicon-nitrides, orcombinations thereof are typically used for the barrier layer 45a. Forexample, TaN, Ta, Ti, TiN, TiSiN, WN, or combinations thereof may beused. In an embodiment, the barrier layer 45a includes a TaN layer and aTa layer, in another embodiment, the barrier layer 45a is a TiN layer.In yet another embodiment, the barrier layer 45a is a Ti layer. Thebarrier layer 45a can be formed using PVD (physical vapor deposition),sputtering, or the like. Subsequently, a metal seed layer (not shown) isformed on the barrier layer 45a. In an embodiment, the metal seed layeris a copper seed layer that may be formed by PVD (physical vapordeposition) sputtering, electro plating, or electroless plating. In someembodiments, other methods for forming the copper seed layer, such asCVD (chemical vapor deposition), are used.

Next, a conductive material layer is deposited on the interposer 20 tofill the TSV opening thereby forming a conductive plug 55. Throughoutthe description, the conductive plug 55 is referred to as athrough-silicon-via (TSV). The conductive material layer may include alow resistivity conductor material selected from the group of conductormaterials including, but is not limited to, copper and copper-basedalloy. In some embodiments, the conductive material layer may comprisevarious materials, such as tungsten, aluminum, gold, silver, titanium,or the like. The formation methods may include sputtering, printing,electroplating, electroless plating, and/or chemical vapor deposition(CVD) methods.

Subsequently, the excess portions of the conductive material layeroutside the ISV TSV opening are removed, either through etching,chemical mechanical polishing (CMP), or the like, having the uppersurface of the conductive plug 55 substantially coplanar with the uppersurface of the liner layer 40.

One or more etch stop layers 60 may optionally be formed over interposer20. Generally, the etch stop layers provide a mechanism to stop anetching process when forming vias and/or contacts. In some embodimentsetch stop layer 60 is formed of a dielectric material having a differentetch selectivity from adjacent layers, e.g., the underlying liner layer40, the substrate 30, and an overlying ILD layer 70. In an embodiment,etch stop layer 60 may be formed of SiN, SiON, ON, combinations thereof,or the like, deposited by CVD or PECVD techniques.

Still referring to FIG. 2, the inter-layer dielectric (ILD) layer 70 isformed on the front surface 32a of substrate 30 over the liner layer 40and the etch stop layer 60. The ILD layer 70 isolates the TSV 55 from asubsequent formation of interconnection structure. The ILD layer 70 maybe a single layer or a multi-layered structure. In some embodiments, theILD layer 70 may be a silicon oxide containing layer formed of doped orundoped silicon oxide by a thermal CVD process or high-density plasma(HDP) process, e.g., undoped silicate glass (USG), phosphorous dopedsilicate glass (PSG) or borophosphosilicate glass (BPSG). In somealternative embodiments, the ILD layer 70 may be formed of doped orP-doped spin-on-glass (SOG), phosphosilicate TEOS (PTEOS), orborophosphosilicate TEOS (BPTEOS).

An interconnect structure electrically connecting the ISV TSV with thesubstrate 30 will now be described with reference to FIGS. 3-6. Withreference to FIG. 3, a via opening 80 is formed extending from the ILDlayer 70 into a portion of the substrate 30. In some embodiments, viaopening 80 may be formed by firstly coating a photoresist layer (notshown) on ILD layer 70. The photoresist layer is then patterned byexposure, bake, development, and/or other photolithography processesusing the patterned photoresist layer as a masking element to form thevia opening. In some embodiments, the via opening 80 may be etched usingany suitable etching method including, for example, a plasma etch, achemical wet etch, a laser drill, and/or other processes. The etchingprocess may result in an opening having a vertical sidewall profile or atapered sidewall profile.

In another embodiment of forming an opening that is a via opening, aphotoresist layer (not shown) may be formed on a hard mask layer (notshown). The photoresist layer is patterned by exposure, bake,developing, and/or other photolithography processes to provide anopening exposing the hard mask layer. The exposed hard mask layer isthen etched, by a wet etch or dry etch process, using the patternedphotoresist layer as a masking element to provide an opening. Using thehard mask layer and the patterned photoresist layer as mask elements, anetching process is performed to etch the exposed substrate 30 formingthe via opening.

A trench opening 90, shown in FIG. 4, is then formed in the ILD layer 70in a similar fashion as forming the via opening 80 above and hence theprocess will not be repeated herein. The trench opening 90 exposes aportion of the TSV 55 so that in a subsequent step a conductive materiallayer will be deposited on interposer 20, said conductive material layerforming an interconnect structure that connects TSV 55 with substrate30. A barrier layer 45b may be formed over interposer 20, in the viaopening 80 and the trench opening 90. A seed layer (not shown) may besubsequently formed over the barrier layer 45b. Both the materials andprocesses used for forming the barrier layer 45b and the seed layer waspreviously described above with reference to FIG. 2 and will thereforenot be described again.

Referring to FIG. 5, the interposer 20 is transferred to a plating tool,such as an electrochemical plating (ECP) tool, and a conductive materiallayer is plated on the interposer 20 by the plating process to fill thevia opening 80 and the trench opening 90 to form an interconnectstructure 100. While the ECP process is described therein, theembodiment is not limited to ECP deposited metal. The conductivematerial layer may include a low resistivity conductor material selectedfrom the group of conductor materials including, but is not limited to,copper and copper-based alloy. In some embodiments, the conductivematerial layer 80 may comprise various materials, such as tungsten,aluminum, gold, silver, or the like. This electroplating process forms avoid-free metallization structure to provide a reliable solution. Othermethods for depositing a conductive material layer in via opening 80 andtrench opening 90 are also contemplated.

Following the depositing of the conductive material layer, the uppersurface of interposer 20 undergoes a planarization step. Excess portionsof the conductive material layer outside the via and trench openings areremoved, either through etching, chemical mechanical polishing (CMP), orthe like, having the upper surface of the interconnect structure 100substantially coplanar with the upper surface of the ILD layer 70.

Advantageously, interposer 20 may be easily customized to suit differentrequirements. In an exemplary embodiment, an active or passive device(not shown) is embedded into the interposer 20, wherein the active orpassive device may include capacitors, resistors, and the like.

It is understood that additional processes may be performed to completethe fabrication of interposer 20 to form various features forimplementation in a semiconductor package structure. Subsequentfabrication processing may further form features such as metal lines,connecting vias, dielectric layers, bonding pads, or solder bumpsconfigured to connect the various features or structures of interposer20 to one or more semiconductor chips. In an exemplary embodiment, asemiconductor chip can be bonded onto interposer 20 with a plurality ofbonding pads. One skilled in the art will realize the correspondingbonding process steps. In another exemplary embodiment, a multi-chipstructure having at least two semiconductor chips can be bonded ontointerposer 20. According to one embodiment, the at least two chips arebonded together before they are bonded onto interposer 20.Alternatively, a first chip is bonded onto interposer 20 first, and thenthe second chip is bonded onto the first chip.

FIG. 6 illustrates another embodiment in which the conductive plug 55 isutilized along with another conductive plug 57, which may also beanother through-silicon via (TSV) or another through-via (TV) in thosecircumstances when the substrate 30 is a non-silicon material. In thisembodiment the another conductive plug 57 may be similar to theconductive plug 55, and may be insulated from the substrate 30 by theline layer 40.

According to one embodiment, a method of forming a semiconductor devicecomprises providing a semiconductor substrate, the semiconductorsubstrate having a first side and a second side opposite the first side;forming a through-silicon via (TSV) opening extending from the firstside of the semiconductor substrate into the semiconductor substrate;forming a liner layer on the first side of the semiconductor substrateand along the sidewalk sidewall and bottom of the TSV opening;depositing a first conductive material layer over the liner layer in theopening to form a TSV; forming an interlayer inter-layer dielectric(ILD) layer over the first side of the semiconductor substrate; forminga via opening extending from the ILD layer into a portion of thesemiconductor substrate; forming a trench opening in the IUD ILD layerto expose a portion of the ISV; and depositing a second conductivematerial layer in the via and the trench openings to form aninterconnect structure, the interconnect structure electricallyconnecting the TSV with the semiconductor substrate.

According to another embodiment, a method of forming an interposercomprises providing a semiconductor substrate, the semiconductorsubstrate having a front surface and a back surface opposite the frontsurface; forming one or more through-silicon vias (TSVs) extending fromthe front surface into the semiconductor substrate; forming aninter-layer dielectric (ILD) layer overlying the front surface of thesemiconductor substrate and the one or more TSVs; and forming aninterconnect structure having a first partition and a second partition,the first partition formed in the ILD layer and the second partitionformed in a portion of the semiconductor substrate, wherein theinterconnect structure electrically connects the one or more TSVs to thesemiconductor substrate.

According to yet another embodiment, an integrated circuit structurecomprises a semiconductor substrate having a front surface and a hacksurface opposite the front surface; a TSV formed extending from thefront surface of the semiconductor substrate into the semiconductorsubstrate; and an interconnect structure having a first partition and asecond partition, the first partition formed in an ILD layer, the ILDlayer overlying the front surface of the semiconductor substrate and thesecond partition formed in a portion of the semiconductor substrate,wherein the interconnect structure electrically connects the TSV to thesemiconductor substrate.

According to yet another embodiment, an interposer comprises asemiconductor substrate having a front surface and a back surfaceopposite the front surface; a TSV formed extending from the frontsurface of the semiconductor substrate into the semiconductor substrate;a liner layer formed at least between the TSV and the semiconductorsubstrate; an ILD layer formed over the front surface of thesemiconductor substrate; and an interconnect structure having a firstpartition and a second partition, the first partition formed in the ILDlayer and the second partition formed in a portion of the semiconductorsubstrate. Wherein the interconnect structure electrically connects theTSV to the semiconductor substrate.

According to yet still another embodiment, a semiconductor packagestructure comprises an interposer having a semiconductor substratehaving a front surface and a back surface opposite the front surface; aTSV formed extending from the front surface of the semiconductorsubstrate into the semiconductor substrate; a liner layer formed atleast between the TSV and the semiconductor substrate; an ILD layerformed over the front surface of the semiconductor substrate; and aninterconnect structure having a first partition and a second partition,the first partition formed in the ILD layer and the second partitionformed in a portion of the semiconductor substrate, wherein theinterconnect structure electrically connects the TSV to thesemiconductor substrate. The package structure further comprises asemiconductor chip; and a plurality of bonding pads bonding thesemiconductor chip to the interposer.

According to yet another embodiment, a semiconductor package structurecomprises an interposer having: a semiconductor substrate having a frontsurface and a back surface opposite the front surface; a TSV formedextending from the front surface of the semiconductor substrate into thesemiconductor substrate; a liner layer formed at least between the TSVand the semiconductor substrate; an ILD layer formed over the frontsurface of the semiconductor substrate; and an interconnect structurehaving a first partition and a second partition, the first partitionformed in the ILD layer and the second partition formed in a portion ofthe semiconductor substrate. Wherein the interconnect structureelectrically connects the TSV to the semiconductor substrate. Thepackage structure further comprises a multi-chip semiconductor structurehaving at least a first chip and a second chip; and a plurality ofbonding pads bonding the semiconductor structure to the interposer.

One or more of the embodiments of the present disclosure discussed abovehave advantages over existing methods. It is understood, however, thatother embodiments may have different advantages, and that no particularadvantage is required for all embodiments.

One of the advantages is that as TSV 55 is grounded (e.g., TSV 55 iselectrically connected to substrate 30), cross coupling and cross talkbetween adjacent TSVs can be minimized. By having the TSVs grounded,resistive-capacitive delays that hinder further increasing of speed inmicroelectronic integrated circuits are minimized and signal integrityis thereby improved. Further, as an added benefit, a grounded TSVprovides for better heat dissipation, especially in micro-electronic ICshaving smaller and smaller feature sizes. As a further advantage bygrounding the TSV, charge build-up on electrostatic discharge (ESD)sensitive integrated circuits from an ESD event is prevented, thusreducing damage to the integrated circuit.

In the preceding detailed description, specific exemplary embodimentshave been described. It will, however, be apparent to a person ofordinary skill in the art that various modifications, structures,processes, and changes may be made thereto without departing from thebroader spirit and scope of the present disclosure. The specificationand drawings are, accordingly, to be regarded as illustrative and notrestrictive. It is understood that embodiments of the present disclosureare capable of using various other combinations and environments and arecapable of changes or modifications within the scope of the claims.

What is claimed is:
 1. A method of forming a semiconductor device,comprising: providing a semiconductor substrate, the semiconductorsubstrate having a first side and a second side opposite the first side;forming a through-silicon via (TSV) opening extending from the firstside of the semiconductor substrate into the semiconductor substrate;forming a liner layer on the first side of the semiconductor substrateand along the sidewalls and bottom of the TSV opening; depositing afirst conductive material layer over the liner layer in the opening toform a TSV; forming an inter-layer dielectric (ILD) layer over the firstside of the semiconductor substrate; forming a via opening extendingfrom the ILD layer into a portion of the semiconductor substrate;forming a trench opening in the ILD layer to expose a portion of theTSV; and depositing a second conductive material layer in the via andthe trench openings to form an interconnect structure, the interconnectstructure electrically connecting the TSV with the semiconductorsubstrate.
 2. The method of claim 1, wherein the semiconductor device isan interposer.
 3. The method of claim 1, after the forming the TSV,further comprising planarizing the first side of the semiconductorsubstrate.
 4. The method of claim 1, further comprising forming a firstbarrier layer between the liner layer and the TSV.
 5. The method ofclaim 4, further comprising forming a first seed layer between the firstbarrier layer and the TSV.
 6. The method of claim 1, before the formingthe ILD layer over the first side of the semiconductor substrate,further comprising forming an etch stop layer.
 7. The method of claim 1,further comprising forming a second barrier layer over the via andtrench openings.
 8. The method of claim 7, further comprising forming asecond seed layer over the second barrier layer.
 9. The method of claim1, wherein the interconnect structure is formed by electro-chemicalplating.
 10. The method of claim 1, wherein the TSV and interconnectstructure comprise copper or copper alloys.
 11. The method of claim 1,after the forming the interconnect structure, further comprisingplanarizing the first side of the semiconductor substrate.
 12. A methodof forming an interposer, comprising: providing a semiconductorsubstrate, the semiconductor substrate having a front surface and a backsurface opposite the front surface; forming one or more through-siliconvias (TSVs) extending from the front surface into the semiconductorsubstrate; forming an inter-layer dielectric (ILD) layer overlying thefront surface of the semiconductor substrate and the one or more TSVs;and forming an interconnect structure having a first partition and asecond partition, the first partition formed in the ILD layer and thesecond partition formed in a portion of the semiconductor substrate,wherein the second partition has straight sidewalls extending from thefirst partition to a bottom of the second partition and wherein theinterconnect structure electrically connecting the one or more TSVs tothe semiconductor substrate.
 13. The method of claim 12, furthercomprising forming a liner layer between at least the one or more TSVsand the semiconductor substrate.
 14. The method of claim 13, furthercomprising forming a barrier layer and/or a seed layer between the oneor more TSVs and the liner layer.
 15. The method of claim 12, furthercomprising forming a barrier layer and/or seed layer between at leastthe interconnect structure and the ILD layer and the front surface ofthe semiconductor substrate.
 16. An integrated circuit structure,comprising: a semiconductor substrate having a front surface and a backsurface opposite the front surface; a through-silicon via (TSV) formedextending from the front surface of the semiconductor substrate into thesemiconductor substrate; and an interconnect structure having a firstpartition and a second partition, the first partition formed in aninter-layer dielectric (ILD) layer, the ILD layer overlying the frontsurface of the semiconductor substrate, and the second partition formedin a portion of the semiconductor substrate and having straightsidewalls from a top surface of the semiconductor substrate to a bottomsurface of the second partition, wherein the interconnect structureelectrically connects the TSV to the semiconductor substrate.
 17. Theintegrated circuit structure of claim 16, wherein the integrated circuitstructure is an interposer.
 18. The integrated circuit structure ofclaim 16, further comprising a liner layer formed at least between theTSV and the semiconductor substrate.
 19. The integrated circuitstructure of claim 18, further comprising: a barrier layer formedbetween the TSV and the liner layer; and a seed layer formed between theTSV and the barrier layer.
 20. The integrated circuit structure of claim16, wherein the interconnect structure and the TSV are formed of thesame conductive material.
 21. The integrated circuit structure of claim17, wherein the interposer comprises passive devices.
 22. The integratedcircuit structure of claim 21, wherein the interposer comprises activedevices.
 23. An interposer, comprising: a semiconductor substrate havinga front surface and a back surface opposite the front surface; athrough-silicon via (TSV) formed extending from the front surface of thesemiconductor substrate into the semiconductor substrate; a liner layerformed at least between the TSV and the semiconductor substrate; aninter-layer dielectric (ILD) layer formed over the front surface of thesemiconductor substrate; and an interconnect structure having a firstpartition and a second partition, the first partition formed in the ILDlayer and the second partition formed in a portion of the semiconductorsubstrate, wherein the interconnect structure electrically connects theTSV to the semiconductor substrate and wherein the second partition hasstraight sidewalls as the second partition extends into thesemiconductor substrate to a bottom surface of the second partition. 24.The interposer of claim 23, further comprising a barrier layer formedbetween the TSV and the liner layer.
 25. The interposer of claim 24,further comprising a seed layer formed between the TSV and the barrierlayer.
 26. The interposer of claim 23, wherein the interconnectstructure and the TSV are formed of the same conductive material. 27.The interposer of claim 23, further comprising passive devices.
 28. Theinterposer of claim 27, further comprising active devices.
 29. Asemiconductor package structure, comprising: an interposer having: asemiconductor substrate having a front surface and a back surfaceopposite the front surface; a through-silicon via (TSV) formed extendingfrom the front surface of the semiconductor substrate into thesemiconductor substrate; a liner layer formed at least between the TSVand the semiconductor substrate; an inter-layer dielectric (ILD) layerformed over the front surface of the semiconductor substrate; and aninterconnect structure having a first partition and a second partition,the first partition formed in the ILD layer and the second partitionformed in a portion of the semiconductor substrate, wherein theinterconnect structure electrically connects the TSV to thesemiconductor substrate, wherein a straight sidewall of the secondpartition extends from a bottom of the second partition to a surface ofthe semiconductor substrate facing the first partition; a semiconductorchip; and a plurality of bonding pads bonding the semiconductor chip tothe interposer.
 30. The semiconductor package structure of claim 29,further comprising an additional semiconductor chip bonded onto thesemiconductor chip.
 31. The semiconductor package structure of claim 29,wherein the interposer comprises passive devices.
 32. The semiconductorpackage structure of claim 31, wherein the interposer further comprisesactive devices.
 33. A semiconductor package structure, comprising: aninterposer having: a semiconductor substrate having a front surface anda back surface opposite the front surface; a through-silicon via (TSV)formed extending from the front surface of the semiconductor substrateinto the semiconductor substrate; a liner layer formed at least betweenthe TSV and the semiconductor substrate; an inter-layer dielectric (ILD)layer formed over the front surface of the semiconductor substrate; andan interconnect structure having a first partition and a secondpartition, the first partition formed in the ILD layer and the secondpartition formed in a portion of the semiconductor substrate, whereinthe interconnect structure electrically connects the TSV to thesemiconductor substrate, the second partition having a straight sidewallthrough the semiconductor substrate; a multi-chip semiconductorstructure having at least a first chip and a second chip; and aplurality of bonding pads bonding the multi-chip semiconductor structureto the interposer.
 34. The semiconductor package structure of claim 33,wherein the interposer comprises passive devices.
 35. The semiconductorpackage structure of claim 34, wherein the interposer further comprisesactive devices.
 36. An integrated circuit structure, comprising: asemiconductor substrate having a front surface and a back surfaceopposite the front surface; a through via (TV) formed in thesemiconductor substrate; a liner layer formed at least between the TVand the semiconductor substrate; and an interconnect structure having afirst partition and a second partition, the first partition formed in aninter-layer dielectric (ILD) layer, the ILD layer overlying the frontsurface of the semiconductor substrate, and the second partition formedwith straight sidewalls in a portion of the semiconductor substrate,wherein the interconnect structure electrically connects the TV to thesemiconductor substrate.
 37. The integrated circuit structure of claim36, wherein the integrated circuit structure is an interposer.
 38. Theintegrated circuit structure of claim 36, further comprising: a firstbarrier layer formed between the TV and the liner layer; and a seedlayer formed between the TV and the first barrier layer.
 39. Theintegrated circuit structure of claim 38, wherein the interconnectstructure comprises a second barrier layer.
 40. The integrated circuitstructure of claim 39, wherein the second barrier layer is in contactwith a top surface of TV.
 41. The integrated circuit structure of claim39, wherein the second barrier layer is in contact with the firstbarrier layer.
 42. The integrated circuit structure of claim 36, whereinthe interconnect structure and the TV are formed of the same conductivematerial.
 43. The integrated circuit structure of claim 37, wherein theinterposer comprises passive devices.
 44. The integrated circuitstructure of claim 43, wherein the interposer comprises active devices.45. The integrated circuit structure of claim 36, wherein the TV isgrounded.
 46. The integrated circuit structure of claim 36, furthercomprising another TV in the semiconductor substrate and being insulatedfrom the semiconductor substrate by the liner layer.
 47. The integratedcircuit structure of claim 36, wherein the liner layer located betweenthe ILD layer and the front surface of the semiconductor substrate isconformal.
 48. An interposer, comprising: a semiconductor substratehaving a front surface and a back surface opposite the front surface; athrough via (TV) formed in the semiconductor substrate; a liner layerformed at least between the TV and the semiconductor substrate; aninter-layer dielectric (ILD) layer formed over the front surface of thesemiconductor substrate; an interconnect structure having a firstpartition and a second partition, the first partition formed in the ILDlayer and the second partition formed in a portion of the semiconductorsubstrate, wherein the interconnect structure electrically connects theTV to the semiconductor substrate, wherein the second partition hasstraight sidewalls within the semiconductor substrate.
 49. Theinterposer of claim 48, further comprising a first barrier layer formedbetween the TV and the liner layer.
 50. The interposer of claim 49,further comprising a seed layer formed between the TV and the firstbarrier layer.
 51. The integrated circuit structure of claim 49, whereinthe second liner comprises a second barrier layer.
 52. The integratedcircuit structure of claim 51, wherein the second barrier layer is incontact with a top surface of TV.
 53. The integrated circuit structureof claim 51, wherein the second barrier layer is in contact with thefirst barrier layer.
 54. The interposer of claim 48, wherein theinterconnect structure and the TV are formed of the same conductivematerial.
 55. The interposer of claim 48, further comprising passivedevices.
 56. The interposer of claim 55, further comprising activedevices.
 57. The integrated circuit structure of claim 48, wherein theTV is grounded.
 58. The integrated circuit structure of claim 48,further comprising another TV in the semiconductor substrate and beinginsulated from the semiconductor substrate by the liner layer.
 59. Theintegrated circuit structure of claim 48, wherein the liner layercomprises a portion between the ILD layer and the front surface of thesemiconductor substrate.
 60. A semiconductor package structure,comprising: an interposer having: a semiconductor substrate having afront surface and a back surface opposite the front surface; a throughvia (TV) formed in the semiconductor substrate; a liner layer formed atleast between the TV and the semiconductor substrate; a dielectric layerformed over the front surface of the semiconductor substrate; and aninterconnect structure having a first partition and a second partition,the first partition formed in the dielectric layer and the secondpartition formed in a portion of the semiconductor substrate, whereinthe interconnect structure electrically connects the TV to thesemiconductor substrate, the second partition extends into thesemiconductor substrate a first length, the second partition having astraight sidewall along the first length; and a semiconductor chipbonded to the interposer.
 61. The semiconductor package structure ofclaim 60, further comprising an additional semiconductor chip bondedonto the semiconductor chip.
 62. The semiconductor package structure ofclaim 60, wherein the interposer comprises passive devices.
 63. Thesemiconductor package structure of claim 62, wherein the interposerfurther comprises active devices.
 64. The integrated circuit structureof claim 60, wherein the semiconductor chip is bonded to the interposerthrough a plurality of bonding pads.
 65. The integrated circuitstructure of claim 60, wherein the TV is grounded.
 66. The integratedcircuit structure of claim 60, further comprising another TV in thesemiconductor substrate and being insulated from the semiconductorsubstrate by the liner layer.
 67. The integrated circuit structure ofclaim 60, wherein the liner layer comprises a portion between thedielectric layer and the front surface of the semiconductor substrate.68. A semiconductor package structure, comprising: an interposer having:a semiconductor substrate having a front surface and a back surfaceopposite the front surface; a through via (TV) in the semiconductorsubstrate; a liner layer formed at least between the TV and thesemiconductor substrate; a dielectric layer formed over the frontsurface of the semiconductor substrate; and an interconnect structurehaving a first partition and a second partition, the first partitionformed in the dielectric layer and the second partition formed withstraight sidewalls extending into a portion of the semiconductorsubstrate, the straight sidewalls extending from a first side of thesecond partition to a second side of the second partition opposite thefirst side of the partition, wherein the interconnect structureelectrically connects the TV to the semiconductor substrate; and amulti-chip semiconductor structure having at least a first chip and asecond chip, wherein at least one of the first chip and the second chipis bonded to the interposer.
 69. The semiconductor package structure ofclaim 68, wherein the interposer comprises passive devices.
 70. Thesemiconductor package structure of claim 69, wherein the interposerfurther comprises active devices.
 71. The integrated circuit structureof claim 68, wherein the first chip is bonded to the interposer througha plurality of bonding pads.
 72. The integrated circuit structure ofclaim 68, wherein the TV is grounded.
 73. The integrated circuitstructure of claim 68, further comprising another TV in thesemiconductor substrate and being insulated from the semiconductorsubstrate by the liner layer.
 74. The integrated circuit structure ofclaim 68, wherein the second chip is bonded onto the first chip.